VHDL is a hardware description language designed to represent the behavior and architecture of a digital electronic system . Its full name is VHSIC 1 Hardware Description Language .
The advantage of such a description lies in its executability: a specification described in VHDL can be verified by simulation before the detailed design is completed. In addition, computer-aided design tools for switching directly from a VHDL functional description to a logic gate scheme have revolutionized the design of digital circuits, ASICs, and FPGAs .
The VHDL language was commissioned in the 1980s by the United States Department of Defense as part of the VHSIC 2 initiative . In an effort to rationalize, the VHDL uses the same syntax used by the Ada language (the latter is also developed by the Department of Defense).
The initial version of VHDL, standard IEEE 1076-1987 , included a wide range of data types, digital (integer, real), logical ( bits , Boolean ), characters, time, plus bit arrays and strings.
One of the main problems was the bit type. Since it can take only 2 values (0, 1), it is impossible to represent the signals of unknown value or the signals at high impedance , as well as the “force” of a signal (weak, strong or zero) . The IEEE 1164 standard defines the type std_logic with 9 possible states. This was adopted in VHDL-93 (second version of the IEEE 1076 standard ).
In order to address the various problems of electronics, the VHDL standard had to evolve. The IEEE Design Automation Standards Committee (DASC) has created IEEE Standard 1076.1 (1999), or VHDL-AMS ( VHDL-Analog and Mixed Systems ).
This new standard is an extension of the existing IEEE 1076-1987 standard . It allows the description and simulation of analog , digital , and mixed circuits (analog and digital). For this purpose, it uses, in addition to the sequential and concurrent instructions, a new type of instructions, called “simultaneous” instructions, which have the value of equations. In practice, more and more simulators implement this extension. By cons, analog synthesis tools associates are still in their infancy 3 .
Positioning in relation to the Verilog
The Verilog language , although very different from the syntactic point of view, responded to similar needs. There is in fact a quasi-equivalence between the two languages, hence the existence of many translation scripts from one to the other. The VHDL language is now the hardware description language mostly used by European companies whereas Verilog is often preferred on the other side of the Atlantic.
Introduction to VHDL
Simulation and synthesis
The purpose of a hardware description language such as VHDL is to facilitate the development of a digital circuit by providing a rigorous method of describing the operation and architecture of the desired circuit. The idea is not to have to (melt) a real component, instead using development tools to check the expected functioning. This language makes it possible to use simulators , whose role is to test the operation described by the designer.
The next step consists in synthesizing this hardware description in order to obtain a component performing the desired functions, using logical elements ( logic gates , flip-flops or registers ). These will be implemented, depending on the technology used, either directly in transistors (in the case of an ASIC ), or based on the programmable elements of the FPGAs . After the synthesis come the phases of:
- Placement: the physical location of the different elements is chosen;
- Routing: the connections between elements are determined.
These two operations must take into account the resources available on the ASIC (surface) or the FPGA (programmable units).
The VHDL has a dual function (simulation and synthesis), only part of the VHDL is synthesized, the other exists only to facilitate the simulation (writing of behavioral models and test benches ). Depending on the hardware and software used, this part may be more or less extensive. In order to obtain synthesizable and portable VHDL, it is therefore necessary to limit oneself to simple constructions, the transcription of which in gates and scales is simple to realize. Standard 1076.6 was initiated to attempt to define a subset of “synthesis” VHDL.
Vhdl is a very useful language. The syntax of the VHDL is taken from the Ada language , whose keywords have been adapted to the hardware design. One of the peculiarities of the VHDL is that it is possible to easily express the parallelism present within a circuit.
In VHDL, any component (in the software sense) is described in two ways:
- The interface with the outside world, described in a section called entity ;
- The implementation itself, described in a section called architecture .
It is therefore the architecture section that contains the description of the desired hardware function:
- Or in the form of a precise structural description of the hardware architecture (the logical gates to be used and their interconnections);
- Or in the form of expected behavior, that is to say, functional oriented.
In the latter case, the description can make use of concurrent instructions , mainly using definitive assignments (
A <= B;which read A receives B but corresponds to a permanent connection of signal B to signal A) conditional (
A <= B when condition else C;which means: A receives B if the condition is true, otherwise C, but any change to B, C or condition has an immediate effect) and selective ( with selector
A <= B when valeur1, C when valeur2, D when others competing version of the selector switch-case of the C language ). As the name implies, concurrent instructions simulate the parallelism of the circuits described. The order of the competing instructions has no impact on the described circuit.
However, when a logical function is too complex to be described by a concurrent instruction, an algorithmic description called process can be substituted for it . Within these processes , the instructions are used, this time, sequential. These are the classical control structures of programming languages ( if-else, case-when, for / while ) that offer the possibility of implementing any algorithm, at least in simulation.
During the simulation, a process is only executed on an explicit trigger, otherwise it is inactive. From a material point of view, a process is a “black box” of which only the behavior is described but not the structure. From a software point of view, a process behaves like an infinite loop, each iteration being triggered by an activity of one of its input signals (included in its sensitivity list). Thus, for and while instructions are not useful for describing counters, contrary to the usual beliefs of beginners in VHDL.
Double sense of the word “sequential”
Instruction “sequential” in a process , opposes instruction “concurrent” (out of a process ) and not combinatory (for the logic described), which is a source of confusion very frequent among beginners. Indeed, it is possible to describe a combinatorial system by a sequential algorithm (
if A=1 then B <= C; else B<=0; end if;corresponds to an AND gate) as one can describe a sequential circuit by a concurrent instruction (
Q <= Q when LE = '1' else D). Only the synchronous sequential circuits (sensitive to the fronts of the clock signal) can only be described with an algorithm activated on the front of the clock.
A signal is not a variable
In a process , one can find assignments of signals or variables. Unlike variables, the signal assignment has no immediate effect. Only the future value of the signal can be changed. By default, it is the value that this signal will take at the next simulation step, which will only become effective after the end of the process . Thus, in a process , after five instructions
A <= A+1;, the signal A is not increased by 5 but only by 1. It is necessary to read
A.futur <= A.présent +1;so that A. is never modified.
Differences with a programming language
The VHDL has two aspects that can be contradictory. When it comes to writing a behavioral model that will simply be simulated, the language is compiled and then executed by the simulator. However, when it comes to describing a circuit that will be created by a synthesizer, the philosophy is significantly different. The synthesis tool, which has to transform all the code provided in a logic gates implementation, is designed to operate in a very square way. It is necessary to be able to provide it with a clear description (the synthesis of which corresponds to the desired architecture) while being as specific as possible (in order to allow the tool to maximize the generated circuit).
For example, if it is desired to generate a combinatorial logic function (independent of any clock), it will be necessary to assign all the outputs to each call of the process, otherwise the synthesis tool, considering that the unassigned outputs retain Their old value, will set D flip-flops at the output of each unassigned output. This solution is then very bad, since it transforms the function into a synchronous logic function, thus dependent on a clock (which is also specified by the synthesis tool, out of designer control).
This difference implies a great deal of work upstream and downstream of the coding, the circuit described must have already been thought before being coded and it must be verified after design, considering the number of doors and the implantation characteristics, in order to Ensure that no description errors are present. These very strong constraints on the programmer lead to the adoption of very strict guidelines and coding methods.
These big differences with a programming language like the C make the VHDL a language apart, closer to the electronics than to the computer. Moreover, it is not uncommon to see microcontroller architectures implemented on FPGAs , which are themselves programmed in assembler or C in the rest of the project.
Software to start in VHDL
Integrated Development Environment
The main manufacturers of programmable logic circuits offer a free but limited version of their tools.
|Xilinx||ISE Webpack 4||Owner, free, unlimited||Yes||Yes||Simulator ModelSim XE Starter free|
|Altera||Quartus II Web Edition 5||Owner, free, 6 months renewable||Yes||Yes||Simulator ModelSim Altera Starter Edition free|
|Lattice||IspLever starter 6||Owner, free, 6 months renewable||Yes||Yes||Synthesizer: Synplify Pro for Lattice (free), Active-HDL Simulator Lattice edition (free)|
|Actel||Libero 7||Owner, free, 1 year renewable||Yes||Yes||Synthesizer: Synplify Pro Actel Edition (free), ModelSim Actel Edition simulator (free)|
|Aldec||Active-HDL Student Edition 8||Owner, free, 1 year||Third Party||Yes|
|Mentor Graphics||ModelSim PE Student Edition 9||Owner, free||No||Yes|
|Dolphin Integration||SMASH 10||Owner, free||No||Yes||Free SMASH Discovery Simulator (with examples in VHDL)|
The above-mentioned development environments all allow the entry of a VHDL file, however some text editors offer advanced features such as syntax highlighting , fully automatic , code folding, or macro-commands . This is the case for the following free software:
- Notepad ++
- Crimson Editor (high-performance column mode)
- Smultron (Mac OSX)
- Gedit (Unix)
- Kwrite (Unix)
Examples of descriptions in VHDL
Some concepts, such as files or time scales, only make sense for the modeling of an electronic component and are not accessible to the component itself. The display of a string on the standard output is also an abstract concept, it is only possible in simulation.
- Declaration of entity entity hello_world is end entity hello_world ; - declaration of architecture architecture wiki of hello_world is begin - Process display_text display_text : process is begin - Display string "Hello world!" On the standard output of the simulator report "Hello world!" ; - Pause the wait process ; End process display_text ; End architecture wiki ;
There are several possible descriptions of a component where one of the outputs changes state after a specified time.
A 4 to 1 multiplexer (three different competitor architectures)
In VHDL, we must distinguish the container from the content, named respectively entity and architecture.
The VHDL file
A VHDL file must always have the name of the entity that it contains (this is a usage rule that helps to clarify, it is even mandatory with some software). Its standard extension is “.vhd”, although we sometimes write “.vhdl”. First of all, you must first declare the use of libraries necessary for the project:
- In VHDL: a line of comments begins with two "-" - It is preferable to first import standard VHDL libraries standardized by the IEEE, because they are often necessary. IEEE library ; use IEEE.std_logic_1164.all ; use IEEE.numeric_std.all ;
Libraries std_logic_arith , std_logic_signed and std_logic_unsigned , despite their name, are not standardized by IEEE and its use is strongly discouraged. Indeed, it is preferable to explicitly specify the type of each vector on which an operation is performed ( SIGNED or UNSIGNED ) so as to specify its arithmetic processing. The conduct of operations on the types STD_LOGIC_VECTOR varies depending on the library called, making their use risky.
Description of the interface (entity) of a multiplexer with four inputs:
- Here's an example of an entity that describes the I / O used - by the three examples of purely competing architectures: - - CAUTION, with some CAD tools, the entity must have the same name as the file (Log_4_vers_1.vhd) ENTITY logic_4_to_1 IS PORT ( a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : IN STD_LOGIC ; d : IN STD_LOGIC ; adr : IN STD_LOGIC_VECTOR ( 1 downto 0 ); s : OUT STD_LOGIC ); END logic_4_to_1 ;
The first architecture to describe this multiplexer uses directly a Boolean formulation, which can be used in practice only for simple equations. This method allows to write any combinatorial function.
- First competing architecture describing a mux: ARCHITECTURE mux_4_vers_1 OF logic_4_vers_1 IS BEGIN s <= ( a AND NOT adr ( 1 ) AND NOT adr ( 0 ) ) OR ( b AND NOT adr ( 1 ) AND adr ( 0 ) ) OR ( c AND adr ( 1 ) AND NOT adr ( 0 ) ) OR ( D AND adr ( 1 ) AND adr ( 0 ) ); END mux_4_vers_1 ;
The second architecture uses the keywords WITH , SELECT, and WHEN . Behavior simulation of such writing may be different from the first when the inputs are set to X or Z .
- Second competing architecture describing a mux: ARCHITECTURE mux_4_vers_1 OF logic_4_vers_1 IS BEGIN WITH adr SELECT s <= a WHEN "00" , b WHEN "01" , c WHEN "10" , d WHEN others ; END mux_4_vers_1 ;
The last line is used to group all cases not explicitly processed into a single line.
The third architecture uses the WHEN and ELSE keywords .
- Third competing architecture describing a mux: ARCHITECTURE mux_4_vers_1 OF logic_4_vers_1 IS BEGIN s <= a WHEN adr = "00" ELSE b WHEN adr = "01" ELSE c WHEN adr = "10" ELSE d ; END mux_4_vers_1 ;
Sequential architecture – a D flip-flop
The description of a sequential architecture, that is to say with the aid of a time-dependent function (ie. The clock) through the use of processes .
- Sequential Architecture for rocking D: ARCHITECTURE comport OF bascule_d IS BEGIN PROCESS ( clk , reset ) BEGIN IF reset = '1' THEN q <= '0' ; ELSE IF clk 'event AND clk = ' 1 ' THEN - Less well than: IF rising_edge (clk) THEN q <= d ; END IF ; END IF ; END process ; END comport ;
- ↑ VHSIC stands for Very High Speed Integrated Circuit .
- ↑ ( en ) Peeter Ellervee, Kalle Tammemäe VHDL – Hardware Description Language [ archive ] [PDF] , Tallinn University of Technology – Department of Computer Engineering, visited 24 September 2008
- ↑ http://www.univ-bpclermont.fr/FORMATIONS/Master/meam/cme/cme02.pdf [ archive ] [PDF] p. 30-47
- ↑ Xilinx ISE WebPACK [ archive ]
- ↑ Quartus II Web Edition Software Version 7.2 [ archive ]
- ↑ ispLEVER Starter [ archive ]
- ↑ Libero [ archive ]
- ↑ Students – Active-HDL Student Edition [ archive ]
- ↑ ModelSim – Technical Resources: ModelSim PE Student Edition Overview [ archive ]
- ↑ SMASH [ archive ]