The Verilog , its full name Verilog HDL is a hardware description language of logic circuits in electronics , used for the design of ASICs ( application-specific integrated circuits , dedicated circuits) and FPGAs ( field-programmable gate array ).
The English acronym HDL – Hardware Description Language – means Hardware Description Language . “Verilog HDL” shall not be abbreviated as VHDL, this abbreviation being used for the competing language VHSIC Hardware Description Language .
Originally, it was a proprietary language developed by Cadence Design Systems [ archive ] for use in their logic simulators , but the growing success of VHDL ( Very High speed integrated circuits Hardware Description Language , Another language with similar objectives) prompted its designers to make Verilog an open standard ; It is the IEEE 1364 standard of which there are several versions, which have been enriched to offer functions equivalent to those of VHDL .
Verilog combines two aspects:
- Simulation: it describes the sequence of events;
- Description by combination of elements (modules, expressions, logic gates, etc.), which makes it possible to synthesize circuits.
Verilog’s syntax is widely believed to be inspired by C programming language , although the resemblance is actually limited to expressions. This explains in part its success and its rapid spread in the community of engineers who have already learned the C language .
The Verilog language structure describes the inputs and outputs of electronic modules to define virtual logic gates. The combination of modules makes it possible to realize complex virtual electronic schemes which can then be tested in a simulation program. The purpose of such tests is to:
- Validate the behavior of the circuits described (the result they deliver is that expected);
- Validate the performances of these circuits (they respond in a given time and the signals that traverse the various modules are correctly synchronized).
Example of Verilog circuit
Here is an example of a logic circuit (here, a counter ) described at the level of register transfer log ( RTL ), that is to say synthesizable:
Module Div20x ( rst , clk , this , vine , count , tc ); // TITLE 'Divide-by-20 Counter with Enables' // enable CEP is a clock enable only // enable CET is a clock and enable // Enables the TC output // a counter using the Verilog language Parameter size = 5 ; Parameter length = 20 ; Input rst ; // These inputs / outputs represent input clk ; // connections to the module. Input this ; Input cep ; Output [ size - 1 : 0 ] count ; Output tc ; Reg [ size - 1 : 0 ] count ; // Signals assigned // within an always // (or initial) block // must be of type reg Wire tc ; // Other signals of type wire // The execution statement that executes anytime the signals // rst or clk transition from low to high always @ ( posedge clk or posedge rst ) if ( rst ) // This causes reset of the cntr count <= 5 'b0 ; Else if ( this && cep ) // Enables both true begin if ( count == length - 1 ) count <= 5 'b0 ; Else count <= count + 5 'b1 ; // 5 ' // the value of tc is continuously assigned // the value of the expression assign tc = ( this && ( count == length - 1 )); Endmodule